1. Field of the Invention
The present invention relates to a protection circuit for a semiconductor integrated circuit, and more particularly, it relates to a circuit for protecting an integrated circuit against high voltage applied to its input terminal.
2. Description of the Prior Art
In a general MIS semiconductor integrated circuit, an input gate of a MIS transistor is extremely weak against electrostatic destruction, and hence a protection circuit is provided between an external connection terminal and an internal circuit to prevent electrostatic destruction, thereby to protect the internal circuit.
FIG. 1 is a circuit diagram including a conventional protection circuit.
Referring to FIG. 1, an inverter circuit 10 having MIS transistors 10a and 10b as an internal circuit 9 is connected with an input bonding electrode 1, a GND (ground) bonding electrode 2 and a V.sub.DD (supply voltage) bonding electrode 3 respectively, and an output voltage V.sub.O is extracted from a junction between the MIS transistors 10a and 10b. A protection circuit 8a is provided between the gates of the MIS transistors 10a and 10b and the input bonding electrode 1. The protection circuit 8a is formed by a protective resistor 4 and a resistor 6 which are connected in series between the input bonding electrode 1 and the internal circuit 9 and an NPN bipolar transistor 7a having a collector which is connected between the protective resistor 4 and the resistor 6 and an emitter and a base which are connected to the GND bonding electrode 2. A parasitic resistance 5a is generated by interconnection thereof between the bipolar transistor 7a and the GND bonding electrode 2.
FIG. 2 is a schematic plan pattern diagram of the bipolar transistor as shown in FIG. 1 and FIG. 3 is a cross sectional view taken along the line III--III in FIG. 2, for typically illustrating wiring etc. Referring to FIGS. 2 and 3, a P-type semiconductor substrate 17 is provided on its major surface with an N.sup.+ -type active layer 14a and a field oxide film 16, an N.sup.+ -type active layer 14b, a field oxide film 16, a P.sup.+ -type active layer 15 and a field oxide film 16 enclosing the same. An input wire 11 is connected to the protective resistor 4 which is connected with the input bonding electrode 1, the N.sup.+ -type active layer 14a and the resistor 6 which is connected with the internal circuit 9 through contacts 13 respectively. A GND wire 12 is also connected to the N.sup.+ -type active layer 14b and the P.sup.+ -type active layer 15 through contacts 13.
The N.sup.+ -type active layers 14a and 14b, the P-type semiconductor substrate 17 and the P.sup.+ -type active layer 15 form the NPN bipolar transistor 7a, such that the N.sup.+ -type active layer 14a serves as the collector, the N.sup.+ -type active layer 14b serves as the emitter and the P-type semiconductor substrate 17 and the P.sup.+ -type active layer 15 serve as the base respectively.
FIG. 4 is a circuit diagram for illustrating the performance characteristic of an NPN bipolar transistor, and FIG. 5 illustrates the volt-ampere characteristic of the bipolar transistor as shown in FIG. 4.
Referring to FIGS. 4 and 5, a DC variable power source 19 and an ammeter 18 are connected in series to a closed circuit connecting an emitter and a collector of a bipolar transistor 7, whose base is connected to the emitter side.
As voltage V is gradually raised from 0V, current I rapidly flows when the voltage exceeds 10.about.12V, although no such current flow is caused if the voltage V is not more than 10.about.12V. This phenomenon is based on a punch through, breakdown or the like. When the voltage V is lowered to the contrary, the current flow is rapidly stopped at 10V, while the current I rapidly flows when the voltage, being further lowered from 0V, is not more than -0.8V. This phenomenon is based on a current in the forward direction. Voltage values are varied with individual NPN bipolar transistors, which show similar characteristics. As hereinbelow described, the NPN bipolar transistor 7 delivers no current with application of low positive voltage but causes a large current flow when the applied voltage exceeds a prescribed level, while causing a large current flow with application of negative voltage, even if the voltage level is low.
On the basis of the aforementioned performance characteristic of the bipolar transistor 7, description is now made on protective operation of the protection circuit 8a as shown in FIG. 1. The protective resistor 4 is adapted to deliver current to cause a large voltage drop, and the resistor 6 is adapted to delay application of high voltage to the internal circuit 9. When positive high voltage is applied to the input bonding electrode 1, current flows from the input bonding electrode 1, through the protective resistor 4, NPN bipolar transistor 7a, and the parasitic resistor 5a to the GND bonding electrode 2 in the case of FIG. 1. When negative high voltage is applied to the input bonding electrode 1, the current flows in the direction exactly opposite to the case of the positive high voltage. As described above, the current flow lowers the voltage applied to the internal circuit 9 thereby protecting the internal circuit 9 from the electrostatic destruction.
FIG. 6 is a schematic plan view showing exemplary positional relation between components relating to conventional protection circuits.
Referring to FIG. 6, input bonding electrodes 1-1 and 1-2 are located in upper and lower positions to be connected to internal circuits 9-1 and 9-2 through protection circuits 8a-1 and 8a-2, respectively. A V.sub.DD bonding electrode 3 is provided in the vicinity of the protection circuit 8a-1 and a GND bonding electrode 2 is provided in the vicinity of the protection circuit 8a-2. The GND bonding electrode 2 is commonly interconnected with the upper and lower protection circuit 8a-1 and 8a-2 through wires generating parasitic resistances 5a-1 and 5a-2 respectively. In such a circuit, the parasitic resistance 5a-1 of the protection circuit 8a-1, being separated from the GND bonding electrode 2, may be larger by about several 1000 times than the parasitic resistance 5a-2 of the protection circuit 8a-2, being close to the GND bonding electrode 2, as the case may be. In this case, the parasitic resistance 5a-1 causes a large voltage drop and a voltage drop by a protective resistor 4 becomes small, whereby the protection circuit 8a-1 is insufficient in ability of extracting high voltage. Thus, the internal circuit 9-1 is lowered in electrostatic destruction resistance.
On the other hand, "Semiconductor Device" in Japanese Patent Laying-Open Gazette No. 85551/1985 discloses technique of discharging electrical charge to a grounding wire by punch through generated on a transistor as a protection circuit when static electricity is applied to an input pad.
Japanese Patent Laying-Open Gazette No. 198762/1984 discloses technique of discharging input excessive voltage to a substrate or the like by a diode before the same is transmitted to a MOSFET.
However, neither literature solves the problem caused by increase in parasitic resistance to be solved by the present invention or suggests a method of solving the problem.